共 50 条
- [41] An auto-zero sample-and-hold circuit in 0.8μm CMOS 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 510 - 513
- [43] A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC 2021 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2021) & 2021 IEEE CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIMEASIA 2021), 2021, : 189 - 192
- [44] A sample-and-hold circuit with very low gain error for time interleaving applications 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, : 456 - 459
- [45] 10 BIT 200MSPS GAAS BIFET SAMPLE-AND-HOLD CIRCUIT ELECTRONICS LETTERS, 1995, 31 (16) : 1335 - 1337
- [46] Front-end Circuit without Sample-and-hold Amplifier for Pipelined ADC Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2020, 47 (10): : 86 - 91
- [47] A low-voltage low-power CMOS sample-and-hold circuit 2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 552 - 555
- [48] A CMOS miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock feedthrough 15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, : 92 - 96
- [50] A precision CMOS sample-and-hold circuit with low temperature drift for integrated transducers 2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, 2004, : 145 - 148