A DELAY INSENSITIVE APPROACH TO THE VLSI DESIGN OF A DRAM CONTROLLER

被引：0

作者：

DEGLORIA, A ^{[1
]}

FARABOSCHI, P ^{[1
]}

OLIVIERI, M ^{[1
]}

机构：

[1] UNIV GENOA,DEPT BIOPHYS & ELECTR ENGN,I-16146 GENOA,ITALY

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1993年 / 37卷 / 1-5期

关键词：

VLSI DESIGN; SELF-TIMED DESIGN; DELAY INSENSITIVE CIRCUITS; DRAM CONTROLLERS;

D O I：

10.1016/0165-6074(93)90007-8

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper presents an application of Delay Insensitive VLSI design to a real case. A Dynamic RAM Controller, matching the specification of the Intel 8202(R) component, has been designed through a delay insensitive methodology, by using a synthesis system developed by the authors. Delay insensitivity is currently a subject of study due to its promising features for VLSI design. Though formal methods have been widely developed, there is a lack of real applications that prove the capabilities of the delay insensitive approach. The main goal of this paper is to show that a delay insensitive methodology is a suitable automated approach to the design of complex VLSI CMOS circuits.

引用

页码：19 / 22

页数：4

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