共 50 条
- [21] Minimizing Differential Crosstalk of Vias for High-speed Data Transmission 2014 IEEE 23RD CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2014, : 191 - 194
- [22] A novel architecture of recovered data comparison for high speed clock and data recovery Noise in Communication Systems, 2005, 5847 : 179 - 187
- [23] A parallel architecture of interpolated timing recovery for high-speed data transfer rate and wide capture-range OPTICAL DATA STORAGE 2007, 2007, 6620
- [24] Hybrid Big Data Architecture for High-Speed Log Anomaly Detection JOURNAL OF INTERNET TECHNOLOGY, 2017, 18 (07): : 1681 - 1688
- [25] A/D Converter Circuit and Architecture Design for High-Speed Data Communication 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013,
- [26] High-speed bulk data transfer architecture for Gbit/s throughput ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS, 2003, 86 (11): : 57 - 65
- [28] A new I/O interface architecture for high-speed data communication IEEE INTERNATIONAL SYMPOSIUM ON COMPUTERS AND COMMUNICATIONS, PROCEEDINGS, 1999, : 216 - 225
- [29] Hybrid Big Data Architecture for High-Speed Log Anomaly Detection 2016 13TH INTERNATIONAL JOINT CONFERENCE ON COMPUTER SCIENCE AND SOFTWARE ENGINEERING (JCSSE), 2016, : 538 - 543