AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY

被引：36
|
作者：
SHUNG, CB
LIN, HD
CYPHER, R
SIEGEL, PH
THAPAR, HK
机构：
[1] AT&T BELL LABS, HOLMDEL, NJ 07733 USA
[2] IBM CORP, ALMADEN RES CTR, DIV RES, SAN JOSE, CA 95120 USA
[3] IBM CORP, DIV STORAGE SYST PROD, SAN JOSE, CA 95114 USA
来源：
IEEE TRANSACTIONS ON COMMUNICATIONS | 1993年 / 41卷 / 04期
关键词：
D O I：
10.1109/26.223789
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The Viterbi algorithm has been widely applied to many decoding and estimation applications in communications and signal processing. A state-parallel implementation is usually used in which one add-compare-select (ACS) unit is devoted to each state in the trellis. In this paper we present a systematic approach of partitioning, scheduling, and mapping the N trellis states to P ACS's, where N > P. The area saving of our architecture comes from the reduced number of both the ACS's and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the area-efficient architecture offers a favorable (smaller) area-time product, compared to a state-parallel implementation. These results will be demonstrated by application examples in the accompanying paper.
引用
收藏
页码：636 / 644
页数：9
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