DESIGN OF A VERY LINEAR CMOS TRANSCONDUCTANCE INPUT STAGE FOR CONTINUOUS-TIME FILTERS

被引：4
|
作者：
VANPETEGHEM, PM
FOSSATI, HM
RICE, GL
LEE, SY
机构：
[1] Department of Electrical Engineering, Texas A&M University, College Station, Systems Integration, IBM Corporation, Houston, TX
[2] Department of Electrical Engineering, Texas A&M University, College Station, TX
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 02期
关键词：
D O I：
10.1109/4.52176
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel CMOS differential input stage for transconductance amplifiers is presented that combines a low noise excess factor (NEF), low input capacitance, and high CMRR with a very good linearity. Measured distortion is only 0.2% for a 1-V rms input signal and only 1% for a 2-V rms input signal, on a test circuit implemented in a standard 3- p.m CMOS process, using ± 5-V supplies. This results in over 85 dB of dynamic range. Applications include high-performance continuous-time filters and linear amplifiers. 0018-9200/90/0400-0497$01.00 © 1990 IEEE
引用
收藏
页码：497 / 501
页数：5
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