MINIMUM-LATENCY ARCHITECTURE;
SPECIAL-PURPOSE VLSI PROCESSOR;
PARALLEL PROCESSING;
COMMUNICATION TIME;
BUS INTERCONNECTION NETWORK;
D O I:
暂无
中图分类号:
TP3 [计算技术、计算机技术];
学科分类号:
0812 ;
摘要:
The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.
机构:
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University, JapanDepartment of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University, Japan
Kim, Bumchul
Kameyama, Michitaka
论文数: 0引用数: 0
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机构:
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University, JapanDepartment of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University, Japan