Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study

被引：5
|
作者：
Abouelatta-Ebrahim, Mohamed [1 ,2 ]
Shaker, Ahmed [1 ]
Sayah, Gihan T. [3 ]
Gontrand, Christian [2 ]
Zekry, Abdelhalim [1 ]
机构：
[1] Ain Shams Univ, Fac Engn, Cairo 11517, Egypt
[2] Univ Lyon, INL, INSA Lyon, UMR5270,CNRS, F-69621 Villeurbanne, France
[3] Nucl Mat Author, Cairo, Egypt
来源：
AIN SHAMS ENGINEERING JOURNAL | 2015年 / 6卷 / 02期
关键词：
nLDMOS; 0.35 mu m BiCMOS; RESURF; Smart power integrated circuit (SPIC); Breakdown voltage; Specific ON-resistance;
D O I：
10.1016/j.asej.2014.12.003
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35 lm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent R-ON,R-SP/BV trade-off (BV approximate to 400 V and R-ON,R-SP 9.5 m Omega cm(2) for T-epi = 4 mu m and L-Drift = 17 mu m) without any added process complexity. The maximum obtained drain current is 1.8 mA/mu m at a gate voltage of 5 V. The designed device is suitable for smart power integration. (C) 2014 Faculty of Engineering, Ain Shams University. Production and hosting by Elsevier B. V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
引用
收藏
页码：501 / 509
页数：9
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