FAULT TOLERANCE IN LINEAR SYSTOLIC ARRAYS USING TIME REDUNDANCY

被引：8
|
作者：
MAJUMDAR, A
RAGHAVENDRA, CS
BREUER, MA
机构：
[1] Electrical Engineering-Systems Department, University of Southern California, Los Angeles
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1990年 / 39卷 / 02期
关键词：
Algorithm remapping; fault tolerance; reliability modeling; systolic array; time redundancy;
D O I：
10.1109/12.45214
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A linear systolic array with fault-tolerant capabilities is de- scribed. Fault tolerance is achieved by employing triple time redundancy. The array is capable of undergoing reconfiguration and can operate in a gracefully degradable mode. The concept of algorithm remapping on degraded (smaller) arrays is integrated with that of graceful degradation to obtain a general fault-tolerance technique. A new technique for restructuring algorithms and executing them on a degraded array is discussed. The requisite modifications of the interconnection, switching, and control structures to achieve fault tolerance are discussed. Reliability analysis of the system is carried out and is compared to the reliability of nonredundant systolic arrays. Finally, the average performance of the system, with running time and throughput as performance metrics, is estimated. © 1990 IEEE
引用
收藏
页码：269 / 276
页数：8
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