A HARDWARE ACCELERATOR FOR HIERARCHICAL VLSI ROUTING

被引：0
|
作者：
RAVIKUMAR, CP
SASTRY, S
机构：
来源：
INTEGRATION-THE VLSI JOURNAL | 1989年 / 7卷 / 03期
关键词：
D O I：
10.1016/0167-9260(89)90006-0
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：283 / 302
页数：20
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