PERFORMANCE AND OPTIMIZATION OF DIPOLE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR

A new class of devices, the Dipole Heterostructure Field Effect Transistors (Dipole HFET's), are proposed and have been fabricated in AlGaAs/GaAs. Doped p++ and n++ planes in the charge control AlGaAs layer form a dipole that creates a considerably larger barrier between the channel and the gate than in conventional heterostructure FET's. This leads to a sharp reduction of the forward-biased gate current in enhancement-mode n-channel devices, a much broader transconductance peak, and a higher maximum drain current in enhancement-mode devices. The paper also outlines an analytical theory, supported by numerical modeling, the optimization of device structures for both enhancement- and depletion-mode devices. This is supported by experimental device results obtained from enhancement devices.