HIGH-SPEED INTERLACED DRO AND NDRO OPERATION OF A PLATED-WIRE MEMORY SYSTEM

被引：0

作者：

FINCH, TR

WAABEN, S

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1968年 / SC 3卷 / 01期

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D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：41 / &

共 50 条

[1] HIGH-SPEED DRO PLATED-WIRE MEMORY SYSTEM
FINCH, TR
WAABEN, S
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1966, MAG2 (03) : 529 - &
[2] HIGH-SPEED INTERLACED WRITE AND READ-ONLY OPERATION OF A PLATED-WIRE MEMORY SYSTEM
WAABEN, S
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1968, C 17 (11) : 1062 - +
[3] HIGH-SPEED PLATED-WIRE MEMORY SYSTEM
WAABEN, S
[J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (03): : 335 - +
[4] PROGRESS REPORT ON DEVELOPMENT OF PLATED-WIRE MEMORY .1. DRO HIGH-SPEED SYSTEM
IHARA, H
HABA, Y
UEKI, I
HOSODA, K
[J]. NEC RESEARCH & DEVELOPMENT, 1971, (23): : 30 - &
[5] CREEPING IN NDRO PLATED-WIRE MEMORY ELEMENTS
YOSHIMI, K
SUZUKI, S
FURUOYA, T
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1970, MAG6 (03) : 637 - &
[6] 106-BIT NDRO PLATED-WIRE MEMORY
ISHI, O
TAKASHIMA, M
TOSAKA, K
NAKAMURA, K
NITTA, M
[J]. ELECTRONICS & COMMUNICATIONS IN JAPAN, 1972, 54 (05): : 104 - +
[7] DRO PLATED-WIRE DEVELOPMENT
ALLEN, GR
BONNIE, GP
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1971, MAG7 (03) : 502 - &
[8] 106-BIT NDRO PLATED-WIRE MEMORY.
Ishi, Osamu
Nitta, Matsuo
Takashima, Minoru
Nakamura, Katsuro
Tosaka, Katsuyuki
[J]. Electronics and Communications in Japan (English translation of Denshi Tsushin Gakkai Zasshi), 1971, 54 (05): : 104 - 112
[9] PROGRESS REPORT ON DEVELOPMENT OF PLATED-WIRE MEMORY .2. NDRO LOW-COST SYSTEM
MATSUMOT.H
HIKI, Y
KUROKAWA, H
[J]. NEC RESEARCH & DEVELOPMENT, 1971, (23): : 41 - &
[10] A 3-DIMENSIONAL OPERATION IN PLATED-WIRE MEMORY
MURAKAMI, H
WADA, Y
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1969, MAG5 (03) : 422 - &

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