PROGRESS REPORT ON DEVELOPMENT OF PLATED-WIRE MEMORY .2. NDRO LOW-COST SYSTEM

被引：0

作者：

MATSUMOT.H

HIKI, Y

KUROKAWA, H

机构：

来源：

NEC RESEARCH & DEVELOPMENT | 1971年 / 23期

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：41 / &

共 50 条

[1] CREEPING IN NDRO PLATED-WIRE MEMORY ELEMENTS
YOSHIMI, K
SUZUKI, S
FURUOYA, T
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1970, MAG6 (03) : 637 - &
[2] 106-BIT NDRO PLATED-WIRE MEMORY
ISHI, O
TAKASHIMA, M
TOSAKA, K
NAKAMURA, K
NITTA, M
[J]. ELECTRONICS & COMMUNICATIONS IN JAPAN, 1972, 54 (05): : 104 - +
[3] 106-BIT NDRO PLATED-WIRE MEMORY.
Ishi, Osamu
Nitta, Matsuo
Takashima, Minoru
Nakamura, Katsuro
Tosaka, Katsuyuki
[J]. Electronics and Communications in Japan (English translation of Denshi Tsushin Gakkai Zasshi), 1971, 54 (05): : 104 - 112
[4] HIGH-SPEED INTERLACED DRO AND NDRO OPERATION OF A PLATED-WIRE MEMORY SYSTEM
FINCH, TR
WAABEN, S
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1968, SC 3 (01) : 41 - &
[5] PROGRESS REPORT ON DEVELOPMENT OF PLATED-WIRE MEMORY .1. DRO HIGH-SPEED SYSTEM
IHARA, H
HABA, Y
UEKI, I
HOSODA, K
[J]. NEC RESEARCH & DEVELOPMENT, 1971, (23): : 30 - &
[6] HIGH-SPEED PLATED-WIRE MEMORY SYSTEM
WAABEN, S
[J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (03): : 335 - +
[7] HIGH-SPEED DRO PLATED-WIRE MEMORY SYSTEM
FINCH, TR
WAABEN, S
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1966, MAG2 (03) : 529 - &
[8] ANNEALING EFFECTS IN PLATED-WIRE MEMORY ELEMENTS, .2. RECRYSTALLIZATION IN PERMALLOY FILMS
MARQUARDT, SJ
KENCH, JR
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1971, MAG7 (04) : 858 - +
[9] A 16-MBIT RANDOM-ACCESS PLATED-WIRE MEMORY SYSTEM
SMALE, BG
[J]. IEEE TRANSACTIONS ON MAGNETICS, 1969, MAG5 (03) : 428 - &
[10] Progress report on the development of the plated- wire memory. A DRO high- speed system- 1
IHARA H
HABA Y
HOSODA K
UEKI I
[J]. NEC Research and Development, 1971, (23): : 30 - 40

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