Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits

被引：1

作者：

Najeebl, K. ^{[1
]}

Gururajl, Karthik ^{[1
]}

Kamakotil, V. ^{[1
]}

Vedula, Vivekananda M. ^{[2
]}

机构：

[1] IIT Madras, Dept Comp Sci & Engn, Madras 600036, Tamil Nadu, India

[2] Intel Corp, Validat & Test Solut Grp, Austin, TX USA

来源：

JOURNAL OF LOW POWER ELECTRONICS | 2007年 / 3卷 / 03期

关键词：

CMOS Circuits; Power Dissipation; Dynamic Peak Power; Automatic Test Pattern Generation (ATPG); Fanout Free Regions;

D O I：

10.1166/jolpe.2007.140

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The problem of peak power estimation in CMOScircuits is essential for analyzing the reliability and performance of them at extreme conditions. The Peak Dynamic Power Estimation (PDPE) problem involves finding input vectors which when applied shall cause maximum dynamic power dissipation (maximum toggles) in digital circuits. In this paper, an approach for generating input vectors for the PDPE problem on both combinational and sequential circuits is presented. The basic intuition behind this approach is to use the 0- and 1-controllability measures of the gate outputs in the circuit to guide a modified version of the conventional D-Algorithm to generate the necessary test vectors. In addition, the input circuit is partitioned into Fanout Free Regions (FFRs). The modified D-Algorithm deals with the FFRs rather than individual gates, thereby enhancing its scalability with increasing design size. The proposed technique was employed on the ISCAS'85, ISCAS'89 and ISCAS'99 benchmark circuits. The results of the above show a significant improvement in power estimation results when compared to the best known existing techniques reported in the literature.

引用

页码：280 / 292

页数：13

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