VLSI IMPLEMENTATION OF A 16-STATE COSET CODE

Calderbank and Sloane [1] have recently introduced a new technique for constructing trellis codes based on lattices and cosets. Codes based on these principles will be referred to in this paper as coset codes. We present a parallel 2μ CMOS VLSI implementation of a particular 16-state coset code described in [1]. The encoder decoder for this code were developed using Path-Programmable Logic (PPL) design methodology [6]. The resulting system occupies four chips and should be able to operate at data rates approaching 50 megabits per second. An alternative design using 1μ CMOS technology could be implemented on two chips and could operate at data rates up to 100 megabits per second. © 1990.