VLSI implementation of DVB/RCS turbo code

In this paper, first different aspects of the implementation issues of the decoder with VLSI are explored, then a complete decoder VLSI design of non-binary convolutional turbo code for DVB/RCS will be presented. With a new normalization approach, the decoder can be speeded up considerably. In order to save area, a practical simplification method of branch metric calculation is introduced, which makes the whole design much more efficient. From an architectural point of view, an optimal full pipelined structure is designed with the forward path metric and backward path metric recursive circuits being optimized for speed and other functions being optimized for area. In the last part of this paper, another pipelined area saving method is proposed. The design is synthesized on a single chip FPGA (Xilinx Virtex-E). According to the RTL level and gate level simulation results and the in-chip test result, the decoder can work up to 7 Mbits/s data rate at 6 iterations with VirtexE. This is constitutes a two fold improvement over currently available products using the same FPGA family.