VLSI IMPLEMENTATION OF A SYSTOLIC DATABASE MACHINE FOR RELATIONAL ALGEBRA AND HASHING

被引：0

作者：

ELLEITHY, KM ^{[1
]}

BAYOUMI, MA ^{[1
]}

DELCAMBRE, LM ^{[1
]}

机构：

[1] UNIV SW LOUISIANA,CTR ADV COMP STUDIES,LAFAYETTE,LA 70504

来源：

INTEGRATION-THE VLSI JOURNAL | 1991年 / 11卷 / 02期

基金：

美国国家科学基金会;

关键词：

DATABASE MACHINES; SYSTOLIC ARRAYS; RELATIONAL ALGEBRA; HASHING; VLSI;

D O I：

10.1016/0167-9260(91)90018-G

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Database machines (DBMs) are motivated by the need for high speed query processing. Systolic arrays provide a promising future implementation for DBMs. A systolic architecture for a DBM capable of performing relational algebra operations is introduced in this paper. The array also supports the basic operations for hashing: member, insert and delete, in constant time. A VLSI implementation using a 3-mu CMOS technology is analyzed. The systolic array is simple because it employs only one basic cell type. Using only one cell type reduces design time and cost and enhances reliability of DBMs.

引用

页码：169 / 190

页数：22

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