CHIP-LEVEL MODELING WITH HDLS

被引：3

作者：

ARMSTRONG, JR ^{[1
]}

机构：

[1] VIRGINIA POLYTECH INST & STATE UNIV,VHDL ANAL & STANDARDIZAT GRP,BLACKSBURG,VA 24061

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1988年 / 5卷 / 01期

关键词：

COMPUTER HARDWARE DESCRIPTION LANGUAGES - FAILURE ANALYSIS;

D O I：

10.1109/54.667

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are presented. HDL code for each model is given to illustrate it use. Fault modeling at the chip level is examined.

引用

页码：8 / 18

页数：11

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