MODULAR DECOMPOSITION OF COMBINATIONAL MULTIPLE-VALUED CIRCUITS

被引：2
|
作者：
FANG, KY [1 ]
WOJCIK, AS [1 ]
机构：
[1] MICHIGAN STATE UNIV,DEPT COMP SCI,E LANSING,MI 48824
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1988年 / 37卷 / 10期
关键词：
D O I：
10.1109/12.5993
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：1293 / 1301
页数：9
相关论文
共 50 条
  • [1] A test algorithm for multiple-valued logic combinational circuits
    Levashenko, V
    Moraga, K
    Kholovinski, G
    Yanushkevich, S
    Shmerko, V
    [J]. AUTOMATION AND REMOTE CONTROL, 2000, 61 (05) : 844 - 857
  • [2] MULTIPLE-VALUED CCD CIRCUITS
    BUTLER, JT
    KERKHOFF, HG
    [J]. COMPUTER, 1988, 21 (04) : 58 - 69
  • [3] Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares
    Niknafs, Aliakbar
    Mohammadi, Majid
    [J]. INTEGRATION-THE VLSI JOURNAL, 2013, 46 (02) : 189 - 196
  • [4] Decomposition of multiple-valued relations
    Perkowski, M
    MarekSadowska, M
    Jozwiak, L
    Luba, T
    Grygiel, S
    Nowicka, M
    Malvi, R
    Wang, Z
    Zhang, JS
    [J]. 27TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - 1997 PROCEEDINGS, 1997, : 13 - 18
  • [5] Synthesis of quantum multiple-valued circuits
    Miller, D. Michael
    Maslov, Dmitri
    Dueck, Gerhard W.
    [J]. JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2006, 12 (5-6) : 431 - 450
  • [6] Multiple-Valued Reversible Logic Circuits
    De Vos, Alexis
    Van Rentergem, Yvan
    [J]. JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2009, 15 (5-6) : 489 - 505
  • [7] CODE ASSIGNMENT ALGORITHM FOR HIGHLY PARALLEL MULTIPLE-VALUED COMBINATIONAL-CIRCUITS BASED ON PARTITION THEORY
    TAMAKI, S
    KAMEYAMA, M
    HIGUCHI, T
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1993, E76D (05) : 548 - 554
  • [8] MODULAR REPRESENTATION OF MULTIPLE-VALUED LOGIC SYSTEMS
    GREEN, DH
    TAYLOR, IS
    [J]. PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON, 1974, 121 (06): : 409 - 418
  • [9] PROSPECTS FOR MULTIPLE-VALUED INTEGRATED-CIRCUITS
    SMITH, KC
    GULAK, PG
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1993, E76C (03) : 372 - 382
  • [10] Test generation for multiple faults in multiple-valued logic circuits
    Pan, ZL
    [J]. ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 618 - 621
12345