FLEXIBLE SYSTOLIC ARCHITECTURE FOR VLSI FIR FILTERS

被引：5

作者：

WYRZYKOWSKI, R ^{[1
]}

OVRAMENKO, S ^{[1
]}

机构：

[1] POLYTECH KIEV,DEPT COMP ENGN 2003,KIEV 56,UKRAINE,USSR

来源：

IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES | 1992年 / 139卷 / 02期

关键词：

ARRAY PROCESSORS; DIGITAL FILTERS; SYSTOLIC ARRAY;

D O I：

10.1049/ip-e.1992.0027

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new systolic array architecture with a spiral structure of interconnections is proposed for very-high-throughput VLSI FIR filters. This architecture consists of L x K cells, where K is the filter order and 1 less-than-or-equal-to L less-than-or-equal-to K. The architecture produces multiple output samples in parallel and allows increase of filter throughput by L times, in comparison with the usual linear arrays consisting of K cells. As a result, high flexibility in the realisation of FIR filters with desired throughputs can be achieved.

引用

页码：170 / 172

页数：3

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