Hardware Architecture for the Implementation of the Discrete Wavelet Transform in two Dimensions

This paper presents a hardware architecture developed by the two-dimensional wavelet transform on an FPGA, in the design it was searched a balance between the number of required logic cells and the processing speed. The design is based on a methodology to reuse the input data with a parallel-pipelined structure and a calculation of the coefficients is perfomed using a method of odd and even numbers, which is achieved by calculating a cycle ratio after 2 cycles latency, to store the data processing result of the SDRAM memory is used IS42S16400. the control unit uses a design architecture supported by Nios II processor. The system was implemented in the FPGA Altera Cyclone II EP2C35F672C6 using a design that combines descriptions in VHDL, schematics and control connection via a general purpose processor.