REACHABILITY OF SAMPLED DATA SYSTEMS WITH INPUT AND OUTPUT DELAYS

被引：0
|
作者：
DIDUCH, CP
DORAISWAMI, R
机构：
[1] Department of Electrical Engineering, University of New Brunswick, Fredericton, NB E3B 5A3
来源：
AUTOMATICA | 1990年 / 26卷 / 02期
关键词：
Control theory; controllability; delays; sampled data systems;
D O I：
10.1016/0005-1098(90)90141-4
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Zero order hold discrete-time models of sampled data plants with multiple input and output delays are derived. The delay is not assumed to be an integral multiple of the sample period, nor is it assumed identical for all inputs or outputs. It is proven that the discrete model is reachable iff (i) the discrete model with zero integral delay is reachable, (ii) the number of plant inputs is greater than or equal to the number of outputs and (iii) there are no transmission zeros at the origin. © 1990.
引用
收藏
页码：425 / 428
页数：4
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