NOVEL RECURSIVE ALGORITHM AND HIGHLY COMPACT SEMISYSTOLIC ARCHITECTURE FOR HIGH-THROUGHPUT COMPUTATION OF 2-D DHT

被引：1
|
作者：
MEHER, PK
PANDA, G
机构：
[1] Department of A.E. & I.E., Regional Engg. College
来源：
ELECTRONICS LETTERS | 1993年 / 29卷 / 10期
关键词：
SIGNAL PROCESSING; VLSI; TRANSFORMS; ALGORITHMS;
D O I：
10.1049/el:19930590
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A recursive algorithm and a fully pipelined semisystolic CORDIC architecture for computing the 2-D discrete Hartley transform are proposed. The proposed architecture has nearly eight times the throughput rate and requires nearly (1/8)th the chip area compared with the existing CORDIC architecture [1].
引用
收藏
页码：883 / 885
页数：3
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