A LAYOUT SYSTEM FOR THE RANDOM LOGIC PORTION OF AN MOS LSI CHIP

被引：0

作者：

SHIRAKAWA, I

OKUDA, N

HARADA, T

TANI, S

OZAKI, H

机构：

[1] SHARP CORP,CTR COMP AIDED DESIGN,NARA,JAPAN

[2] NIPPON ELECT CO LTD,DIV TRANSMISS,KAWASAKI 211,JAPAN

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1981年 / 30卷 / 08期

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：572 / 581

页数：10

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