共 19 条
- [1] A RECONFIGURATION ALGORITHM FOR DELAY MINIMIZATION IN VLSI/WSI ARRAY PROCESSORS [J]. MICROPROCESSING AND MICROPROGRAMMING, 1987, 20 (1-3): : 127 - 132
- [3] Fault-tolerant array processors via reconfiguration of two-level redundancy arrays [J]. INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-III, PROCEEDINGS, 1997, : 1633 - 1642
- [4] Reconfiguration Algorithm for Low Temperature Sub-array on VLSI/WSI Arrays with Faults [J]. 2011 18TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2011,
- [5] ALUMINUM 2-LEVEL INTERCONNECTION FOR VLSI [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1982, 129 (03) : C104 - C104
- [6] ASSIGNMENT OF JOBS TO PROCESSORS IN A 2-LEVEL SYSTEM [J]. CYBERNETICS, 1988, 24 (02): : 211 - 217
- [9] FAULT-TOLERANT VLSI SYSTOLIC ARRAYS AND 2-LEVEL PIPELINING [J]. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1983, 431 : 143 - 158