DONT CARE SET SPECIFICATIONS IN COMBINATIONAL AND SYNCHRONOUS LOGIC-CIRCUITS

We present a unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits. We characterize such circuits in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. We model the replacement of a gate in a synchronous logic network by a perturbation of the corresponding logic function, and show that the don't care conditions for the gate optimization represent the bound on this perturbation. We present algorithms to compute such don't care conditions in both the combinational and synchronous case. We comment on the implementation of the algorithms and on the experimental results.