SIMULTANEOUS EXTRACTION OF HOLE BARRIER HEIGHT AND INTERFACIAL OXIDE THICKNESS OF POLYSILICON-EMITTER BIPOLAR-TRANSISTORS

A simple method to extract simultaneously the hole barrier height chi-p and interfacial oxide layer thickness delta of polysilicon emitter bipolar transistor is extended. A non-linear chi-square fit method is employed. Both rectangular and parabolic barrier analytical models are examined and are used in the extraction. In the limit of rectangular barrier, the parabolic-barrier model converges to the rectangular-barrier model. The ideal part of the measured base current-voltage characteristics is used in the extraction process. It is found that the extracted hole barrier height and interfacial oxide layer thickness are in good agreement with published results.