CURRENT SOURCES FOR EMITTER-COUPLED LOGIC-CIRCUITS AND THEIR APPLICATION TO SUB-NANOSECOND LOGIC INTEGRATED-CIRCUITS

被引：0

作者：

TANIGUCHI, K ^{[1
]}

HAYASAKA, A ^{[1
]}

KAJI, T ^{[1
]}

YUMOTO, O ^{[1
]}

机构：

[1] HITACHI LTD,CENT RES RES LAB,KOKUBUNJI,TOKYO 185,JAPAN

来源：

ELECTRONICS & COMMUNICATIONS IN JAPAN | 1977年 / 60卷 / 12期

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：118 / 127

页数：10

共 50 条

[1] EMITTER-COUPLED INTEGRATED-CIRCUITS AND THEIR APPLICATION IN NANOSECOND NUCLEAR ELECTRONICS (SURVEY)
BASILADZE, SG
[J]. INSTRUMENTS AND EXPERIMENTAL TECHNIQUES, 1976, 19 (06) : 1589 - 1604
[2] FEEDTHROUGH IN EMITTER-COUPLED LOGIC CIRCUITS
RABBAT, NB
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, SC10 (02) : 97 - 105
[3] ADVANCED DEVELOPMENTS IN SUB-NANOSECOND INTEGRATED LOGIC CIRCUITS
NARUD, JA
SEELBACH, WC
[J]. ELECTRONIC ENGINEERING, 1969, 43 (497): : 17 - &
[4] FEEDTHROUGH IN EMITTER-COUPLED LOGIC CIRCUITS - COMMENT
ROSENBERGER, FU
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (06) : 545 - 545
[5] LOGIC INTEGRATED-CIRCUITS
MURRAY, J
[J]. ENGINEERING, 1975, 215 (09): : R1 - R8
[6] GALLIUM-ARSENIDE INTEGRATED-CIRCUITS FOR THE SUB-NANOSECOND REGION
KRAVCHENKO, LN
SAPELNIKOV, AN
STAROSELSKII, VI
[J]. SOVIET MICROELECTRONICS, 1980, 9 (05): : 219 - 229
[7] MODELING AND ANALYSIS OF BRIDGING FAULTS IN EMITTER-COUPLED LOGIC (ECL) CIRCUITS
MENON, SM
JAYASUMANA, AP
MALAIYA, YK
CLINKINBEARD, DR
[J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1993, 140 (04): : 220 - 226
[8] MULTICHANNEL NANOSECOND-RANGE LOGIC-CIRCUITS
BASILADZE, SG
SHA, NT
[J]. INSTRUMENTS AND EXPERIMENTAL TECHNIQUES, 1980, 23 (02) : 430 - 433
[9] LOGIC TESTING OF INTEGRATED-CIRCUITS
ROBACH, C
SAUCIER, G
[J]. ONDE ELECTRIQUE, 1978, 58 (12): : 842 - 849
[10] SIMULATING LOGIC-CIRCUITS - A MULTIPROCESSOR APPLICATION
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HALSTEAD, RH
[J]. INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 1987, 16 (04) : 305 - 338

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