MEMORY ACCESS DEPENDENCIES IN SHARED-MEMORY MULTIPROCESSORS

被引:32
|
作者
DUBOIS, M
SCHEURICH, C
机构
[1] Department of Electrical Engineering—Systems, University of Southern California, Los Angeles
基金
美国国家科学基金会;
关键词
Cache-based systems; combining networks; memory coherence; ordering of events; parallel algorithms; sequential consistency; shared-memory multiprocessors;
D O I
10.1109/32.55094
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
A multiprocessor system designed to support multithreading must adhere to a simple logical model of concurrency. Besides executing each process correctly, the multiprocessor must preserve the dependencies among processes. Dependencies among concurrent processes are specified by explicit statements such as critical sections or by the sharing of writable data. Parallelizing compilers and programmers using concurrent languages must conform to the model of concurrency of the machine, to generate correct code. The presence of high-performance mechanisms in shared-memory multiprocessors, such as private caches, extensive pipelining of memory accesses and combining networks may render a logical concurrency model complex to implement or inefficient. In this paper, the problem of implementing a given logical concurrency model in a multiprocessor is addressed. Two concurrency models are considered, and simple rules are introduced to verify that a multiprocessor architecture adheres to the models. The rules are applied to several examples of multiprocessor architectures. © 1990 IEEE
引用
收藏
页码:660 / 673
页数:14
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