共 50 条
- [3] TEST-GENERATION FOR DIGITAL CIRCUITS DESCRIBED BY MEANS OF REGISTER TRANSFER LANGUAGES [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1987, 134 (02): : 69 - 77
- [4] Generation of test patterns for defect and noise in VLSI circuits using binary decision diagrams [J]. FIFTH INTERNATIONAL SYMPOSIUM ON INSTRUMENTATION SCIENCE AND TECHNOLOGY, 2009, 7133
- [5] AUTOMATIC TEST-GENERATION FOR DIGITAL ELECTRONIC-CIRCUITS [J]. AT&T TECHNICAL JOURNAL, 1994, 73 (02): : 19 - 29
- [6] Automatic test pattern generation for functional RTL circuits using assignment decision diagrams [J]. 37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, : 43 - 48
- [7] TEST-GENERATION FOR CIRCUITS DESCRIBED IN PROCEDURAL HARDWARE DESCRIPTION LANGUAGES (HDLS) [J]. MICROPROCESSING AND MICROPROGRAMMING, 1986, 18 (1-5): : 371 - 379
- [8] AN AUTOMATIC TEST-GENERATION SYSTEM FOR LARGE DIGITAL CIRCUITS [J]. IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (05): : 54 - 60
- [9] Timing simulation of digital circuits with binary decision diagrams [J]. DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 460 - 466
- [10] FUNTEST - FUNCTIONAL TEST-GENERATION FOR VLSI-CIRCUITS AND SYSTEMS [J]. MICROELECTRONICS AND RELIABILITY, 1989, 29 (03): : 357 - 364