A GENERAL-PURPOSE CMOS ASSOCIATIVE PROCESSOR IC AND SYSTEM

被引：0
|
作者：
STORMON, CD
TROULLINOS, NB
SALEH, EM
CHAVAN, AV
BRULE, MR
OLDFIELD, JV
机构：
[1] SYRACUSE UNIV,DEPT COMP & INFORMAT SCI,SYRACUSE,NY 13244
[2] SYRACUSE UNIV,DEPT ELECT & COMP ENGN,SYRACUSE,NY 13244
[3] SYRACUSE UNIV,CASE CTR,SYRACUSE,NY 13244
来源：
IEEE MICRO | 1992年 / 12卷 / 06期
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An associative processor architecture integrates the functionality of content-addressable memory, functional memory, and associative parallel processors in a single-chip architecture. We combined a set of 16 such chips to form the Coherent Processor, which interfaces to an IBM PS/2 computer. The processor's writable control store permits quick execution of application-specific microcoded operations.
引用
收藏
页码：68 / 78
页数：11
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