A SUBLITHOGRAPHIC ANTIFUSE STRUCTURE FOR FIELD-PROGRAMMABLE GATE ARRAY APPLICATIONS

被引：4

作者：

CHEN, KL ^{[1
]}

LIU, DKY ^{[1
]}

MISIUM, G ^{[1
]}

GOSNEY, WM ^{[1
]}

WANG, SJ ^{[1
]}

CAMP, J ^{[1
]}

TIGELAAR, H ^{[1
]}

机构：

[1] SO METHODIST UNIV,DEPT ELECT ENGN,DALLAS,TX 75275

来源：

IEEE ELECTRON DEVICE LETTERS | 1992年 / 13卷 / 01期

关键词：

D O I：

10.1109/55.144949

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter demonstrates an antifuse structure with a cell area of 0.2 x 0.2-mu-m2 which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2-mu-m lithographic capability will be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse.

引用

页码：53 / 55

页数：3

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