EFFECTS OF INSITU THERMAL ANNEALING ON DEFECTS ASSOCIATED WITH GAAS/GE INTERFACE IN GAAS/GE/SI HETEROSTRUCTURE

Effects of in-situ annealing during and after Ge buffer layer growth on the behavior of line defects at the GaAs/Ge interface of GaAs/Ge/Si heterostructure grown by molecular beam epitaxy were investigated using transmission electron microscopy. Results show that threading dislocations toward the GaAs layers were blocked more efficiently at the Ge/GaAs interface when in-situ thermal annealing for 10 min at 750-degrees-C was performed after Ge buffer layer growth, and also for a similar heat treatment applied between the growth of Ge layers. Neither stacking faults nor microtwins were observed in the samples studied, probably because the surface morphology of the Ge buffer layer improved due to in-situ thermal annealing suppressing the nucleation of the planar defects and the use of a tilted substrate surface so as to minimize the number of the single-atom steps.