共 50 条
- [1] A circuit partitioning algorithm under path delay constraints APCCAS '98 - IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: MICROELECTRONICS AND INTEGRATING SYSTEMS, 1998, : 113 - 116
- [4] A circuit partitioning algorithm with path delay constraints for multi-FPGA systems IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1997, E80A (03): : 494 - 505
- [5] On multilevel circuit partitioning 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 505 - 511
- [6] A CIRCUIT PARTITIONING ALGORITHM IZVESTIYA VYSSHIKH UCHEBNYKH ZAVEDENII RADIOELEKTRONIKA, 1984, 27 (03): : 74 - 76
- [7] Multilevel circuit partitioning DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1997, 1997, : 530 - 533
- [9] CIRCUIT PARTITIONING SIMPLIFIED IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1988, 35 (01): : 2 - 5