Low-Area Wallace Multiplier

被引：6

作者：

Asif, Shahzad ^{[1
]}

Kong, Yinan ^{[1
]}

机构：

[1] Macquarie Univ, Dept Engn, Sydney, NSW 2109, Australia

来源：

VLSI DESIGN | 2014年

关键词：

D O I：

10.1155/2014/343960

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Multiplication is one of the most commonly used operations in the arithmetic. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. A number of modifications are proposed in the literature to optimize the area of the Wallace multiplier. This paper proposed a reduced-area Wallace multiplier without compromising on the speed of the original Wallace multiplier. Designs are synthesized using Synopsys Design Compiler in 90 nm process technology. Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers. The speed of the proposed and reference multipliers is almost the same.

引用

页数：6

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