A New approach to Detect Safety Violations in UML Statechart Models

被引:0
|
作者
Prashanth, C. M. [1 ]
Shet, K. Chandrashekar [1 ]
机构
[1] Natl Inst Technol Karnataka, Dept Comp Engn, Surathkal, India
关键词
UML Statecharts; Software verification; Reactive Systems;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The model based development is a widely accepted phenomenon to build reliable software. This has prompted development of tools capable of generating code from the model. Such rapid software development tools are handy in development of embedded systems. The code generated using tools can be deployed directly on to target hard ware, provided the model correctness is ensured. In this paper, we present an efficient procedure to verify UML (Unified Modeling Language) statechart models of reactive and concurrent systems. The algorithm checks for safety property violation during the construction (on-the-fly) of the state space graph and generates counter example if any violation is found. The exploration of the state space is terminated, as soon as safety violation is found and hence search space is reduced. We prove the correctness of the approach by taking a benchmark case study of Generalized Railroad Crossing (GRC) system. The dynamic behavior of the gate & track, two concurrent objects of the GRC system are modeled using UML statecharts and the safety property "when train is at the crossing, the gate always remain closed" is verified. We could detect property violation in the initial UML statechart model of GRC and later it is corrected with the help of the counter example generated by the algorithm. The case study results show that the verification algorithm yields 13% reduction in the state space for the GRC example.
引用
收藏
页码:167 / 174
页数:8
相关论文
共 50 条
  • [41] Representing and reasoning on fuzzy UML models: A description logic approach
    Ma, Z. M.
    Zhang, Fu
    Yan, Li
    Cheng, Jingwei
    EXPERT SYSTEMS WITH APPLICATIONS, 2011, 38 (03) : 2536 - 2549
  • [42] A systematic approach to generate inputs to test UML design models
    Dinh-Trong, Trung T.
    Ghosh, Sudipto
    France, Robert B.
    ISSRE 2006:17TH INTERNATIONAL SYMPOSIUM ON SOFTWARE RELIABILITY ENGINEERING, PROCEEDINGS, 2006, : 95 - +
  • [43] Towards a Hybrid Approach to Measure Similarity Between UML Models
    Goncales, Lucian Jose
    Farias, Kleinner
    Bischoff, Vinicius
    PROCEEDINGS OF THE XV BRAZILIAN SYMPOSIUM ON INFORMATION SYSTEMS, SBSI 2019: Complexity on Modern Information Systems, 2019,
  • [44] A Logic-Based Approach for the Verification of UML Timed Models
    Baresi, Luciano
    Morzenti, Angelo
    Motta, Alfredo
    Pourhashem, Mohammad Mehdi K.
    Rossi, Andmatteo
    ACM TRANSACTIONS ON SOFTWARE ENGINEERING AND METHODOLOGY, 2017, 26 (02)
  • [45] Validation and automatic test generation on UML models: the AGATHA approach
    David Lugato
    Céline Bigot
    Yannick Valot
    Jean-Pierre Gallois
    Sébastien Gérard
    François Terrier
    International Journal on Software Tools for Technology Transfer, 2004, 5 (2-3) : 124 - 139
  • [46] A digital twin internal to a PLC to detect malicious commands and ladder logic that potentially cause safety violations
    Werth, Aaron W.
    Morris, Thomas H.
    Journal of Cyber Security Technology, 2023, 7 (02) : 53 - 82
  • [47] A New Approach to Model Checking of UML State Machines
    Niewiadomski, Artur
    Penczek, Wojciech
    Szreter, Maciej
    FUNDAMENTA INFORMATICAE, 2009, 93 (1-3) : 289 - 303
  • [48] A new approach to automatically detect worms
    Wang, P
    Fang, BX
    Yun, XC
    PDCAT 2005: Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, Proceedings, 2005, : 259 - 263
  • [49] A state-based approach to integration testing based on UML models
    Ali, Shaukat
    Briand, Lionel C.
    Rehman, Muhammad Jaffar-ur
    Asghar, Hajra
    Iqbal, Muhammad Zohaib Z.
    Nadeem, Aamer
    INFORMATION AND SOFTWARE TECHNOLOGY, 2007, 49 (11-12) : 1087 - 1106
  • [50] An Approach to Generate Safety Validation Test Cases from UML Activity Diagram
    Tiwari, Saurabh
    Gupta, Atul
    2013 20TH ASIA-PACIFIC SOFTWARE ENGINEERING CONFERENCE (APSEC 2013), VOL 1, 2013, : 189 - 198