PERFORMANCE ANALYSIS OF INTERCONNECTION NETWORKS OF A MODIFIED-MODEL FOR SYNCHRONOUS MULTIPROCESSORS

被引：0
|
作者：
POMBORTSIS, A
HALATSIS, C
机构：
[1] Univ of Thessaloniki, Digital, Systems & Computers Lab,, Thessaloniki, Greece, Univ of Thessaloniki, Digital Systems & Computers Lab, Thessaloniki, Greece
来源：
ELECTRONICS LETTERS | 1986年 / 22卷 / 04期
关键词：
D O I：
10.1049/el:19860155
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The letter presents an analysis of a modified model for synchronous multiprocessor systems. In this model, besides the shared memory modules, each processor has a private memory. The memory references of each processor are not uniformly distributed among the memory modules. The interconnection network is considered to be either a crossbar or a shared bus.
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页码：222 / 224
页数：3
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