LOGIC SYNTHESIS FOR LIBRARY-BASED FIELD-PROGRAMMABLE GATE ARRAYS

The emergence of Field-Programmable Gate Arrays (FPGAs) as an important new technology to implement digital systems requires specific CAD methods. In this paper we propose logic synthesis techniques developed for FPGA technologies with large libraries. To map Boolean functions to an FPGA technology, several graph based representations of Boolean functions are investigated for their suitability. We also propose two approaches to exploit functional degrees of freedom before and after technology mapping. Experimental results for benchmark circuits show the effectiveness of the various synthesis and optimization techniques.