SUPPRESSION OF ARSENIC AUTODOPING WITH RAPID THERMAL EPITAXY FOR LOW-POWER BIPOLAR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR

Scaled bipolar transistors for bipolar complementary metal oxide semiconductor (BiCMOS) integrated circuits require low collector-substrate capacitance in order to minimize power consumption. The unintentional incorporation of dopant into a growing epitaxial layer, known as autodoping, can affect the ultimate lower limit of the collector-substrate capacitance. In this work, we studied the effects of epitaxial layer growth rate, arsenic-buried layer implant dose, and pre-epitaxial bake temperature on autodoping using rapid thermal epitaxy (RTE). To begin, we experimented with the buried layer implant dose to check its affect on lateral autodoping. The amount of autodoping increased when the buried layer implant dose increased, confirming the source of the arsenic autodoping as the buried layer. Also, in contrast to data from conventional reactors, we found the peak interface concentration and integrated dose in regions adjacent to the buried layer to be Linearly dependent on the growth rate (i.e., low growth rates trap less arsenic at the substrate/epi layer interface) for all growth rates studied. Next, by adjusting the prebake temperature over a range from 800 to 1050 degrees C without changing the growth conditions, we first observed a rise in autodoping with temperature to 950 degrees C, at which point the incorporated autodoping dose and peak concentration began to fall. Through simulation of the evaporated arsenic from the buried layer and data for arsenic desorption from the silicon surface, we explain this behavior. Finally, using the data gathered on the autodoping characteristics of RTE, we show a process using two growth rate steps and a low temperature prebake step which completely eliminates the lateral autodoping peak. Using this new growth process, epitaxial silicon films over arsenic-doped buried layers for low power BiCMOS are possible.