DESIGN OF A GAAS REDUNDANT DIVIDER

被引：0
|
作者：
MOUSSA, I
SKAF, A
GUYOT, A
机构：
来源：
VLSI 93 | 1994年 / 42卷
关键词：
PERFORMANCE ANALYSIS AND DESIGN AIDS; NUMERICAL ALGORITHMS AND PROBLEMS;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a fast combinatorial circuit for performing division Q := A divided by D. High speed is achieved by a new algorithm implemented in Gallium Arsenide (GaAs). An n bit divider produces an n bit quotient Q in 9*n NOR-gate-delay-units, with n(2) add/sub cells (called tail) driven by n controller cells (called head). The divider has been implemented by using a buffering technique and a full custom layout methodology, which are well suited for high performance design in GaAs direct coupled FET Logic (DCFL).
引用
收藏
页码：63 / 72
页数：10
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