DESIGN OF A GAAS REDUNDANT DIVIDER

This paper presents a fast combinatorial circuit for performing division Q := A divided by D. High speed is achieved by a new algorithm implemented in Gallium Arsenide (GaAs). An n bit divider produces an n bit quotient Q in 9*n NOR-gate-delay-units, with n(2) add/sub cells (called tail) driven by n controller cells (called head). The divider has been implemented by using a buffering technique and a full custom layout methodology, which are well suited for high performance design in GaAs direct coupled FET Logic (DCFL).