TRADE-OFFS IN SCAN PATH AND BIST IMPLEMENTATIONS FOR RAMS

被引：0

作者：

NICOLAIDIS, M

KEBICHI, O

ALVES, VC

机构：

[1] Reliable Integrated Systems group, TIMA/INPG, Grenoble Cédex, 38031

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 1994年 / 5卷 / 2-3期

关键词：

ALIASING; BIST; COUPLING FAULTS; RAM TEST ALGORITHMS; SCAN PATH; SIGNATURE ANALYSIS;

D O I：

10.1007/BF00972087

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.

引用

页码：273 / 283

页数：11

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