Analysis of gate tunnelling currents in nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs) with SiO(2)and high-K gate dielectrics

In this paper, an analytical model for gate tunnelling current has been deployed by solving the Schrodinger equation using the Wentzel-Kramer-Brillouin approximation method for a trapezoidal potential barrier. The gate tunnelling current has been computed for direct tunnelling from channel to gate as well as for tunnelling from source drain extension region to gate. The effect of temperature variation on gate tunnelling current with an SiO2 thickness of 4 nm down to 1 nm has been studied at various gate voltages. Gate tunnelling in the case of high-K gate dielectrics and high-K stacks has also been analysed. In order to study the effect of temperature on gate tunnelling current in SiO2 and in high-K dielectrics, the related parameters have been modelled based on physics. The effect of variation of substrate doping concentration (Na) on gate tunnelling current in an n-type metal-oxide-semiconductor field effect transistor (n-MOSFET) with SiO2 has also been studied These studies have been used to bring out the design margins available in equivalent oxide thickness and Na.