A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm

被引：0

作者：

Patri, Sreehari Rao ^{[1
]}

Prasad, K. S. R. Krishna ^{[1
]}

机构：

[1] Natl Inst Technol, Elect & Commun Engn Dept, Chip Design Cener, Warangal 506004, Andhra Prades, India

来源：

VLSI DESIGN | 2008年

关键词：

D O I：

10.1155/2008/259281

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a capacitor-less LDO with improved steady-state response and reduced transient overshoots and undershoots. The novelty in this approach is that the regulation is improved to a greater extent by the improved error amplifier in addition to improved transient response against five vital process corners. Also entire quiescent current required is kept below 100 mu A. This LDO voltage regulator provides a constant 1.2 V output voltage against all load currents from zero to 50 mA with a maximum voltage drop of 200 mV. It is designed and tested using Spectre, targeted to be fabricated on UMC 180 nm. Copyright (C) 2008 S. R. Patri and K. S. R. Krishna Prasad.

引用

页数：7

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