Ultra-wideband (UWB) CMOS power amplifier design and implementation

This paper presents the design and implementation of three power amplifiers (PAs) for 3.1 to 4.8GHz UWB communication system in 0.18 mu m CMOS technology. The proposed PAs are biased with a single 1V DC power supply. The first PA, a single-stage amplifier achieves a maximum power gain of + 7.05dB at 3.25GHz, an input P1dB of - 5.1dBm and output IP3 of + 12dBm at 4GHz, while consuming 21mW of DC dissipation. The second PA is a two-stage amplifier and it has + 13.5dB of maximum gain at 3.2GHz, -2.5dBm of input P1dB and + 16dBm of output IP3 at 4GHz, with a power consumption of 28.3mW. The final PA, a two-stage cascode amplifier has a maximum gain of 14.7dB, input P1dB of -9.1dBm and output IP3 of + 13dBm at 4GHz, consuming 20.2mW from the 1V supply. Measurement results obtained are used to create a nonlinear power-dependent S-parameter (P2D) file that serves as a behavioural model used to determine the optimum input and output matching required for each PA. Finally, advanced simulations with the UWB modulated test signals in the envelope domain, including simulations and analysis of output spectrum and channel power using the created P2D PA models are also illustrated.