A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR

This paper presents a design of 14-bit 80 Msample/s pipelined ADC implemented in 0.35 mu m CMOS. A charge-sharing correction is proposed to remove the signal-dependent charge-injection, together with a low-jitter clock circuit, guaranteeing the high dynamic performance for the ADC. A scheme of capacitor-switching and a symmetrical layout technique minimizes capacitor mismatch, ensuring the overall linearity. The measured results show that the calibration-free ADC achieves an effective number of bits of 11.6-bit, spurious free dynamic range (SFDR) of 84.8 dB, signal-to-noise-and-distortion ratio (SNDR) of 72 dB, differential nonlinearity of +0.63/-0.6 LSB and integrated nonlinearity of +1.3/-0.9 LSB at 36.7 MHz input and maintains over 75 dB SFDR and 59 dB SNDR up to 200 MHz.