DESIGN AND PERFORMANCE ANALYSIS OF AN ASYNCHRONOUS BANYAN NETWORK SWITCH WITH WINDOW POLICY

被引:1
|
作者
LEE, GY
UN, CK
机构
来源
IEE PROCEEDINGS-COMMUNICATIONS | 1995年 / 142卷 / 02期
关键词
NETWORKS; SWITCHING ARCHITECTURE;
D O I
10.1049/ip-com:19951811
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The authors propose an architecture of an asynchronous banyan network switch with window policy. The switch operates asynchronously, and it can transmit packets of any length at any bit time. When a packet has a collision inside the switch and is blocked, the failure signal is transferred to the input controller which originated the packet. Hence there is no loss of packets in the switch. The switch has a significant advantage in that a window scheme can be implemented. The asynchronous switch with a window scheme yields significant improvement of the maximum throughput as compared with the synchronous banyan network with no window scheme. The authors analyse the maximum throughput of the asynchronous switch with finite window size. In the analysis they make some approximations. The analytical results have been verified by simulation.
引用
收藏
页码:54 / 60
页数:7
相关论文
共 50 条
  • [11] Sliding-banyan network performance analysis
    Haney, MW
    Christensen, MP
    APPLIED OPTICS, 1997, 36 (11): : 2334 - 2342
  • [12] Optical switch array using banyan network
    Okayama, H
    Okabe, Y
    Kamijoh, T
    Sakamoto, N
    IEICE TRANSACTIONS ON COMMUNICATIONS, 1999, E82B (02) : 365 - 372
  • [13] Optical switch array using Banyan network
    Oki Electric Industry, Co, Ltd, Hachioji-shi, Japan
    IEICE Trans Electron, 2 (313-320):
  • [14] Optical switch array using Banyan network
    Okayama, H
    Okabe, Y
    Kamijoh, T
    Sakamoto, N
    IEICE TRANSACTIONS ON ELECTRONICS, 1999, E82C (02) : 313 - 320
  • [15] The Dual-Banyan (DB) switch: A high-performance buffered-banyan ATM switch
    Kolias, C
    Kleinrock, L
    ICC'97: 1997 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS - TOWARDS THE KNOWLEDGE MILLENNIUM, CONFERENCE RECORD - VOLS 1-3, 1997, : 770 - 776
  • [16] A 0.8-MU-M BICMOS ATM SWITCH ON AN 800-MB/S ASYNCHRONOUS BUFFERED BANYAN NETWORK
    SAKAUE, K
    SHOBATAKE, Y
    MOTOYAMA, M
    KUMAKI, Y
    TAKATSUKA, S
    TANAKA, S
    HARA, H
    MATSUDA, K
    KITAOKA, S
    NODA, M
    NIITSU, Y
    NORISHIMA, M
    MOMOSE, H
    MAEGUCHI, K
    ISHIBE, M
    SHIMIZU, S
    KODAMA, T
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (08) : 1133 - 1144
  • [17] NEURAL NETWORK DESIGN OF A BANYAN NETWORK CONTROLLER
    BROWN, TX
    LIU, KH
    IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1990, 8 (08) : 1428 - 1438
  • [18] PERFORMANCE OF DILATED BANYAN NETWORK WITH RECIRCULATION
    YOUN, YS
    UN, CK
    ELECTRONICS LETTERS, 1993, 29 (01) : 62 - 63
  • [19] PERFORMANCE ANALYSIS AND DESIGN OF BANYAN NETWORK BASED BROAD-BAND PACKET SWITCHES FOR INTEGRATED TRAFFIC
    SHAIKH, SZ
    SCHWARTZ, M
    SZYMANSKI, TH
    DALLAS GLOBECOM 89, VOLS 1-3: COMMUNICATIONS TECHNOLOGY FOR THE 1990S AND BEYOND, 1989, : 1154 - 1158
  • [20] Design and performance evaluation of a banyan network based interconnection structure for ATM switches
    Oktug, SF
    Caglayan, MU
    IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1997, 15 (05) : 807 - 816