TIMING-DRIVEN LAYOUT OF CELL-BASED ICS

被引：0

作者：

TEIG, S ^{[1
]}

SMITH, RL ^{[1
]}

SEATON, J ^{[1
]}

机构：

[1] TANGENT SYST CORP,TANCELL CELL BASED IC DESIGN SYST,SANTA CLARA,CA

来源：

VLSI SYSTEMS DESIGN | 1986年 / 7卷 / 05期

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：63 / &

共 50 条

[1] Integrated timing-driven approach to the FPGA layout
Danek, M
Muzikár, Z
[J]. ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 693 - 696
[2] Timing-driven pin assignment with improvement of cell placement in standard cell layout
Wakabayashi, S
Koide, T
[J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 1552 - 1555
[3] An efficient timing-driven global routing method for standard cell layout
Koide, T
Suzuki, T
Wakabayashi, S
Yoshida, N
[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1996, E79D (10) : 1410 - 1418
[4] Timing-driven floorplanning algorithm for Building Block Layout
Kong, TM
Hong, XL
[J]. FOURTH INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN AND COMPUTER GRAPHICS, 1996, 2644 : 477 - 482
[5] Timing-Driven Steiner Tree Construction for Three-Dimensional ICs
Yan, Jin-Tai
Chen, Zhi-Wei
Hu, Dun-Hao
[J]. 2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2008, : 333 - 336
[6] A novel and efficient timing-driven global router for standard cell layout design based on critical network concept
Jing, T
Hong, XL
Bao, HY
Cai, YC
Xu, JY
Gu, J
[J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS, 2002, : 165 - 168
[7] Timing-driven via placement heuristics for three-dimensional ICs
Pavlidis, Vasilis F.
Friedman, Eby G.
[J]. INTEGRATION-THE VLSI JOURNAL, 2008, 41 (04) : 489 - 508
[8] Timing-driven placement based on monotone cell ordering constraints
Hwang, Chanseok
Pedram, Massoud
[J]. ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 201 - 206
[9] Timing-driven cell layout de-compaction for yield optimization by critical area minimization
Iizuka, Tetsuya
Ikeda, Makoto
Asada, Kunihiro
[J]. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 882 - +
[10] TIGER: An efficient timing-driven global router for gate array and standard cell layout design
Hong, XL
Xue, TX
Huang, J
Cheng, CK
Kuh, ES
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (11) : 1323 - 1331

← 1 2 3 4 5 →