Integrated timing-driven approach to the FPGA layout

被引：0
|
作者：
Danek, M [1 ]
Muzikár, Z [1 ]
机构：
[1] Czech Tech Univ, Dept Comp Sci & Engn, Prague 12135 2, Czech Republic
来源：
ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a new timing-driven approach to the FPGA layout synthesis. The approach uses a global routing to assess the quality of a (partial) placement. The placement and routing algorithms use a unified nonlinear cost function that eliminates the effects of different signal net routing orders while taking into account both area and delay constraints imposed by a design.
引用
收藏
页码：693 / 696
页数：4
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