A FAMILY OF USER-PROGRAMMABLE PERIPHERALS WITH A FUNCTIONAL UNIT ARCHITECTURE

被引:3
|
作者
SHUBAT, AS [1 ]
TRINH, CQ [1 ]
ZALIZNYAK, A [1 ]
ZIKLIK, A [1 ]
ROY, A [1 ]
KAZEROUNIAN, R [1 ]
CEDAR, Y [1 ]
EITAN, B [1 ]
机构
[1] WAFERSCALE INTEGRAT INC,DEVICE TECHNOL GRP,FREMONT,CA 94538
关键词
D O I
10.1109/4.126539
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2-mu-m CMOS EPROM process which includes an NVM module that provides the dedicated cells for the EPROM (10.6-mu-m2), PLD, and the configuration bits. The die size is 46 mm2 (for PSD2, which contains 512-kb EPROM) and is housed in a 44-pin package. Memory access time through the PLD is 120 ns and the PLD pin-to-pin delay is 35 ns at 4.5 V and 75-degrees-C.
引用
收藏
页码:515 / 529
页数:15
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