A 500-MEGABYTE/S DATA-RATE 4.5M DRAM

被引：0
|
作者：
KUSHIYAMA, N
OHSHIMA, S
STARK, D
NOJI, H
SAKURAI, K
TAKASE, S
FURUYAMA, T
BARTH, RM
CHAN, A
DILLON, J
GASBARRO, JA
GRIFFIN, MM
HOROWITZ, M
LEE, TH
LEE, V
机构：
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 1993年 / E76C卷 / 05期
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暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In order to improve system bus bandwidth, a novel, small-swing, synchronous bus, which is based on a block-transfer-oriented protocol, has been proposed. A 4.5M DRAM that interfaces to the bus directly and provides a 500-megabyte/s data rate has been developed.
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页码：830 / 838
页数：9
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